Very Large Scale Integrated (VLSI) circuits are designed with the use of Electronic Design Automation (EDA) tools, also called Computer Aided Design (CAD) tools. Various EDA tools are used to generate a netlist. A netlist defines components and interconnections between components required to implement the functional operation of a circuit. A netlist may be formed with a synthesis tool. Alternately, a netlist may be derived from a circuit schematic.
Once a netlist has been generated, there are a number of commercially available place and route tools, also called silicon compilers, which are used to convert the netlist into a semiconductor circuit layout. The semiconductor circuit layout specifies the physical implementation of the circuit in silicon, or some other semiconductive material.
Commercially available tools allow a designer varying degrees of control over the semiconductor circuit layout. A full-custom layout tool allows for full-custom layout of transistor components. Accordingly, a circuit may be highly optimized for a given parameter (e.g., size, power consumption, and the like). Full-custom layout ensures maximum performance. However, this performance comes at a cost. Working at this level of granularity requires a skilled designer and is time-consuming. Therefore, this approach is expensive. In addition, the resulting design is not easily ported to a technology with different physical parameters (e.g., transistor sizes, metal widths and spacings). Consequently, porting an existing full-custom design to a different technology can yield a substantially new layout after a time-consuming and expensive design process.
In contrast to full-custom layout, place and route tools support designing circuits with “standard cells.” Standard cells allow the design layout to be composed at the gate level as opposed to the transistor level. Therefore, designing with standard cells allows one to design at a higher level of abstraction compared to the full-custom layout case. The higher level of abstraction results in design efficiencies, even though granular design control is lost.
Examples of standard cells include simple logic gates, such as inverters, NAND gates, and NOR gates. Standard cells may also include storage elements, such as latches and flip-flops. Standard cells may also include more complex compositions, such as multiplexers, AND_OR INVERT gates, and multiplexing latches. They are called standard cells because collectively they compose a “standard” library of base cells from which designs can be composed. When implemented in silicon, each cell has a standard physical dimension. This allows the cells to be aligned with one another to form standard cell tracks.
FIG. 1 illustrates a prior art standard cell configuration. The figure illustrates a first Vss power rail 20, a Vdd power rail 22, and a second Vss power rail 24. Three standard cells (Cell_1, Cell_2, and Cell_3) are positioned between the first Vss power rail 20 and the Vdd power rail 22. The distance between power rails, the rail-to-rail distance, is fixed throughout the standard cell region. This rail-to-rail distance dictates one standard physical dimension for all of the standard cells. On the other hand, the length of a standard cell along the rail axis is variable. As shown in FIG. 1, Cell_1 (e.g., a NAND gate), has a different axial length than Cell_2 (e.g., a latch). Similarly, Cell_3 (e.g., an adder) has a larger axial length than Cell_2. The same random axial length sizing can also be observed in connection with Cell_4 and Cell-5, positioned between Vdd power rail 22 and second Vss power rail 24.
To simplify FIG. 1, connections between the standard cells (Cell_1 through Cell_5) and the power rails 20, 22, and 24 are omitted. Also, signal tracks running over or beneath the standard cells are omitted for simplification. However, it should be appreciated that power connections and signal track connections to the standard cells are part of the design.
As shown in FIG. 1, standard cell designs commonly result in random layouts with irregular axial length sizing. In addition, standard cell designs commonly have poor line routing between connected standard cells. For example, signal lines regularly extend across different power rails instead of being constrained to the standard cells positioned between one set of power rails. Highly structured designs are conducive to compact and efficient line routing schemes, yet such schemes are rarely achieved in standard cell designs because existing techniques do not allow for significant design constraints that result in layout regularity.
Advantageously, standard cell designs are portable to new technologies. Generating a layout in a new technology only requires the porting of the standard cell library and re-running the place and route tool. While these porting operations are far superior to the porting operations available in a full-custom layout, the resulting circuits are often inefficient, unpredictable, and cannot meet the speed requirements necessary in high-performance designs, particularly in datapaths and similar structures. Many of these shortcomings stem from the inefficient routing of signal lines, as discussed above.
In view of the foregoing, it would be highly desirable to provide an improved electronic design automation technique. In particular, it would be desirable to provide a technique that supplies the design flexibility and compactness of a full-custom layout approach, while providing the simplicity and portability of a standard cell approach.